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Boustras, G, Bratskas, R, Tokakis, V and Efstathiades, A (2011) Safety awareness of practitioners in the Cypriot manufacturing sector. Journal of Engineering, Design and Technology, 9(01), 19–31.
Bullen, P and Love, P (2011) Factors influencing the adaptive re-use of buildings. Journal of Engineering, Design and Technology, 9(01), 32–46.
Dhandapani, K and Sathi, R R (2011) Embedded controlled low-frequency AC to high-frequency AC converter fed induction heater. Journal of Engineering, Design and Technology, 9(01), 7–18.
Ghiasi, V, Omar, H, Huat, B B K, Muniandi, R and Yusof, Z B M (2011) Risk management overview of tunnels using numerical modelling. Journal of Engineering, Design and Technology, 9(01), 110–24.
Harran, M (2011) Dominant feedback practices: shaping engineer literacy perceptions. Journal of Engineering, Design and Technology, 9(01), 85–109.
Jayaram, S and Gonzalez, E (2011) Design and construction of a low-cost economical thermal vacuum chamber for spacecraft environmental testing. Journal of Engineering, Design and Technology, 9(01), 47–62.
Sharma, D K, Kaushik, B K and Sharma, R K (2011) VLSI interconnects and their testing: prospects and challenges ahead. Journal of Engineering, Design and Technology, 9(01), 63–84.
- Type: Journal Article
- Keywords: delay circuits; integrated circuit technology; modelling; tests and testing
- ISBN/ISSN: 1726-0531
- URL: https://doi.org/10.1108/17260531111121477
- Abstract:
Purpose – The purpose of this paper is to explore the functioning of very-large-scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects. Design/methodology/approach – In the past, on-chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring-up of on-chip devices takes place through various conductors produced during fabrication process. The shrinking size of metal-oxide semiconductor field effect transistor devices is largely responsible for growth of VLSI circuits. With deep sub-micron (DSM) technology, the interconnect geometry is scaled down for high wiring density. The complex geometry of interconnects and high operational frequency introduce wire parasitics and inter-wire parasitics. These parasitics causes delay, power dissipation, and crosstalk that may affect the signal integrity in VLSI system. Accurate analysis, sophisticated design, and effective test methods are the requirement to ensure the proper functionality and reliability of VLSI circuits. The testing of interconnect is becoming important and a challenge in the current technology. Findings – The effects of interconnect on signal integrity, power dissipation, and delay emerges significantly in DSM technology. For proper performance of the circuit, testing of interconnect is important and emerging challenge in the nanotechnology era. Although some work has been done for testing of interconnect, however, it is still an open area to test the parasitics effects of VLSI/ultra-large-scale integration interconnects. Efforts are required to analyze and to develop test methods for crosstalk, delay and power dissipation in current technology with solutions to minimize this effect. Originality/value – This paper reviews the functioning of VLSI interconnects from micrometer to nanometer technology. The development of various interconnect models from simple short circuit to latest resistance inductance capacitance transmission line model are discussed. Furthermore, various methodologies such as built-in self test and other techniques for testing interconnect for crosstalk and delay are discussed.